“Chips first” packaging structures are discussed in detail in commonly assigned U.S. Pat. No. 5,841,193 by Charles W. Eichelberger entitled, “Single Chip Modules, Repairable Multichip Modules, and Methods of Fabrication Thereof,” the entirety of which is hereby incorporated herein by reference. The major approaches to chips first packaging (which are described therein) are the Advance Multichip Module (AMCM) approach, and the High Density Interconnect (HDI) approach, along with its off-shoots including the Plastic Encapsulated MCM. In each of these structures, the chips are covered by a layer of polymer that contains via holes down to interconnection pads on the underlying integrated circuit (IC) chips. Metallization is applied and patterned to provide an interconnect layer on the polymer above the IC chips and also to provide connection to the bond pads of the IC chips themselves.
More particular to the present invention, the problem addressed herein relates to the alignment carrier which is used in the fabrication process of single and multichip modules. In the above-incorporated U.S. Pat. No. 5,841,193, methods for adhesively bonding multiple bare (i.e., unpackaged) IC chips to an alignment carrier are disclosed. In one method, an alignment carrier is formed by coating a glass plate with a hot melt adhesive. Subsequently, back grinding tape is bonded to the hot metal adhesive using double sided adhesive tape. Integrated circuit chips are then attached to the adhesive side of the back grinding tape. One problem with this alignment carrier approach is that the pick and place machine which places the IC chips on the back grinding tape must apply excessive pressure to obtain satisfactory wet out of the adhesive. This is because the adhesive cannot be allowed to flow readily or it would not hold the chips once accurately positioned.
In addition, when the structural filler material of the process described in U.S. Pat. No. 5,841,193 is dispensed and cured, it tends to shrink. This shrinkage puts additional stress on the various alignment carrier materials between the glass plate and the IC chips. This stress tends to pull the IC chips towards the center of the alignment carrier displacing them from the original accurate positioning of the pick and place equipment. The amount of displacement has been found to be too variable to compensate accurately so that the net accuracy of placement of the chips suffers.
The problem addressed herein, therefore, is to provide an alignment carrier and process which accurately holds the IC chips in position throughout the subsequent packaging steps and which requires low pressure to set the IC chips during the pick and place operation.
A further problem addressed herein relates to stresses on the input/output (I/O) bumps of Flip Chips, Chip Scale Packages, and interposers for Ball Grid Array (BGA) packages. Specifically, these bumps connect from the pads on, for example, a Flip Chip or Chip Scale Package to a printed circuit board by soldering to pads on the printed circuit board. The printed circuit board is usually an FR4-type board which has an expansion coefficient of 10 to 20 ppm per degree C. depending on the amount of copper wiring employed and other board configuration parameters. In comparison, a silicon integrated circuit (IC) chip has an expansion coefficient of 2–4 ppm per degree C. As a result of this mismatch, thermal stresses can be set up which tend to fatigue the bump or the material surrounding the bump. After several thermal cycles the solder or adjacent material can fail resulting in an open circuit.
The earliest known process of the type described above is the IBM C4 process in which small solder balls are built up directly on the pads of an IC chip. The chip is then inverted and soldered to pads on a circuit board. This process works well when the substrate is well matched to the silicon IC. Such substrates as silicon or alumina have expansion coefficients of 2 to 6 ppm. When this process is done on an FR4 substrate using large chips (1 to 2 cm) less than 100 thermal cycles can be achieved before failure. To minimize this effect, a process is often used where an epoxy material is caused to flow under the chip to bond the chip to the substrate. This distributes the stresses and increases the number of thermal cycles to failure by an order of magnitude. Two problems exist with this process. First, this so called under-fill process requires time consuming steps of deposition and vacuum flow followed by curing. Second, if a chip is bad it cannot be removed once the under-fill has been applied and cured.
Another alternative is to use solder balls which are large in diameter or height so that the differential expansion is amortized over the length of the solder and the 1% strain limit is not exceeded. (It has been found that if solder strain is kept below 1% during temperature cycling then the number of thermal cycles that the solder can endure without fatigue failure is in the 100 to 1000 cycle range.) The problem in this case is that large solder balls take up a large amount of space which is not usually available on the surface of an IC chip. Various techniques have been developed for screen printing large solder balls or columns but these have the same problem that the solder foot print is large and limits the number of I/O available for a given chip size. In addition, when the part is removed usually some solder remains on the circuit board and some solder remains on the part. This adds a requirement for completely cleaning the solder from the circuit board pads before replacing the part.
Another approach is provided by Tessera Inc. of San Jose, Calif., in which a Kapton “flex circuit” layer is placed over a compliant layer on the IC chip. The compliant layer decouples the chip from the Kapton “flex circuit” layer. The Kapton “flex circuit” connects to the circuit board but does not communicate the expansion differential back to the IC chip since the compliant layer is interspersed between the IC chip and the Kapton “flex circuit”. In the Tessera approach, wire or ribbon bonding is used to make connection from the edge of the Kapton circuit layer to the bond pads of the chip. This precludes wiring channels in the area above the bond pads of an IC and thereby limits the number of bond pads which can be accommodated. The approach is expensive because it is not well integrated. It really consists of several components: the Kapton circuit layer, the wire bond or ribbon interconnect, the compliant material and an encapsulant to hold the whole system together. This leads to expensive serial processing steps to connect up the package. (However, the approach does address the problem of thermal mismatch and Tessera chip scale packages can be attached to FR4 circuit boards without under-fill.)
To address the deficiencies of the above processes, presented herein are certain novel structures and methods of fabrication which maintain the strain on the solder or interconnection bumps between a first and second electrical structure to a level lower than the desired 1% level.